The present invention relates to provision of insulator materials having improved dielectric and mechanical properties for semiconductor manufacturing. More specifically, the invention relates to novel materials and methods for applying such materials in the manufacture of semiconductor electronic products.
As the density of semiconductor process integration continues to increase the aggregate amount and compactness of multilevel interconnect on complex integrated circuits is also escalating. With feature sizes and spacings becoming smaller, the speed of a semiconductor device is becoming less dependent on the switching characteristics of individual transistors and more dependent on electrical properties of the interconnect structure. Specifically, because the speed of a signal propagating on interconnect circuitry varies inversely with line resistance and capacitance, semiconductor interconnect requirements are presently considered one of the most demanding aspects of ultra large-scale integration (ULSI) efforts. That is, conductors providing lower resistivity are sought to increase current density, and insulator materials having lower dielectric constants are desired to reduce circuit capacitance.
Thus, as devices of growing complexity are manufactured at smaller geometries, there is motivation to use Cu metallization schemes instead of Al interconnect and efforts have been undertaken to find substitutes for silicon oxide-based insulators. Note, silicon oxides, among the most common of insulator materials used in semiconductor devices, have a dielectric constant of 3.9 or higher (relative to free space), the value depending in part on moisture content.
It is becoming necessary to develop new insulator materials having lower dielectric constants in order to maintain and improve electrical performance characteristics. In particular, efforts to reduce resistance-capacitance (RC) time delays and capacitive coupling have resulted in greater use of so-called xe2x80x9clow kxe2x80x9d dielectrics, i.e., insulative materials characterized by relatively low dielectric constants relative to silicon oxides.
As geometries have extended below the 0.25 micron regime and move toward 0.1 micron, the thermal and mechanical properties of low k dielectrics are of limited compatibility with current manufacturing processes, e.g., chemical-mechanical polishing (CMP). For example, due to desired porosity which helps decrease the dielectric constant, the formation of these materials on a semiconductor structure has resulted in mechanical properties that are not well-suited for CMP. That is, the dielectric material, which is typically spun-on (in the case of a polymer) or deposited (if an inorganic dielectric), is known to be a relatively soft or flaky material such that there is insufficient control during the polish step.
Accommodations to bring soft and flaky low-k dielectrics into volume manufacture include depositing a more rugged cap dielectric material over the low k material in order to utilize established process equipment. For example, hydrogen silsesquioxane (k=3, approx., relative to free space), a strong candidate for replacing silicon dioxide, has high thermal stability, excellent gap-fill properties, and low current leakage. Nonetheless, because the material is not suitable for standard CMP, volume manufacture has required that an overcoat of silicon oxide, formed by Plasma Enhanced Chemical Vapor Deposition (PECVD), be applied prior to the CMP operation and polishing is limited to this cap layer. Also, although use of a cap material will permit CMP processing, this may at times be sub-optimal for high performance circuitry. That is, having a significantly higher dielectric constant, the cap oxide can influence electrical circuit properties. On the other hand, provisions of a low k dielectric material which does not require a cap oxide can result in a simpler process for manufacturing semiconductor devices and enable improved circuit performance at lower cost.
Two of the most important properties for successful implementation of low k materials in processes below 0.2 micron are adhesion (to dissimilar materials) and mechanical toughness (for CMP). Certain forms of hydrogen silsesquioxane can exhibit dielectric constants of approximately 1.5 by controlling the void volume. They also exhibit relatively good adhesion to other materials such as metal bond pads and differing dielectric materials. Of course these favorable results may depend largely on optimized process conditions, e.g., the satisfactory cleaning of surfaces prior to formation of the dielectric thereon, but these characteristics appear attainable in a volume manufacturing environment. In contrast to the advancements made in performance and materials compatibility, manufacturable solutions which accommodate the mechanical properties of low k dielectrics have been generally limited to provision of oxide cap polishing layers. A low-k dielectric material which does not require provision of a relatively hard cap layer having a high dielectric constant thereon will simplify manufacture and improve performance of multi-level interconnect schemes.
Generally, a solution to the aforementioned problems is now provided by a material having both a low dielectric constant and mechanical properties suitable for CMP operations. The invention enables relatively simple and cost efficient placement of insulative material having a low dielectric constant between interconnect members of a circuit structure. According to one embodiment of the invention a porous insulator material comprises oxygen, 25 to 35 atomic percent silicon and 5 to 15 atomic percent hydrogen, and has a density less than 2 g/cc. Alternately, a layer, with oxygen, silicon and hydrogen in the stated compositional ranges, has a refractive index less than 1.45 for light at a wavelength between 633 nm and 673 nm.
In other embodiments, a device is formed along a surface of a semiconductor layer with an interconnect structure providing electrical contact to the transistor device. The interconnect structure includes first and second conductive elements and a dielectric layer positioned to provide isolation between portions of the conductive elements. The dielectric layer, comprises oxygen, at least 25 atomic percent silicon and 5 to 15 atomic percent hydrogen and has a refractive index less than 1.45 for light at a wavelength between 633 and 673 nm. In another form of the invention, a dielectric layer having oxygen, silicon and hydrogen in the stated compositional ranges has a wet etch ratio relative to thermally grown silicon dioxide ranging from 4:1 to 20:1 in an etchant comprising dilute HF.
There is also provided an embodiment with a semiconductor structure including a first upper level of interconnect members formed over a semiconductor layer, at least one lower level of interconnect members formed between the semiconductor layer and the first upper level, and a porous layer of insulative material comprising: oxygen; at least 25 atomic percent silicon; and 5 to 15 atomic percent hydrogen. The porous layer is characterized by a Young""s modulus less than 45 GPa and is positioned to electrically isolate members of the first upper level from members of the lower level. Alternately the porous layer is characterized by a density less than 2 g/cc.
According to one embodiment of a method for manufacturing a semiconductor device, a semiconductor layer has an upper surface and multiple levels of interconnect are formed over the semiconductor layer, each level including at least one conductive member. The members are electrically isolated from other members by decomposition of TEOS to form a dielectric layer of density less than 2 g/cc between the members.
Also according to the invention, a porous layer of insulative material is formed between two levels of interconnect members on a semiconductor structure. The layer includes oxygen, at least 25 atomic percent silicon and 5 to 15 atomic percent hydrogen. In one form the layer includes a continuous distribution of voids throughout the majority of the layer volume.